The present invention relates generally to the field of integrated circuit testing and more specifically to an electron beam test probe system for measuring the potentials on integrated circuits.
Improvements in the design and fabrication of integrated circuits now make it possible to construct integrated circuits with literally millions of transistors and tens of millions of conductors joining these transistors. This level of complexity in integrated circuits has led to significant difficulties in debugging a newly designed integrated circuit. These difficulties can best be described in the context of the following example which describes the typical steps carried out to create a new integrated circuit.
The process normally begins with a design engineer inputting the proposed circuit into a computer simulation program. The cost of design errors can be quite large if such errors are not detected until after the integrated circuit in question has been fabricated. Hence, circuit simulation programs are used to test the circuit. The SPICE program developed at the University of California at Berkeley, California is typical of such simulation programs. The integrated circuit in question is constructed from one or more circuit elements such as transistors. Using a design work station, each of these elements is inputted to the simulation program together with the interconnections between these elements. The interconnection list is often referred to as a NET list. The behavior of each of the circuit elements when various potentials are applied to specified terminals on the element in question is also inputted to the simulation program.
If the results of the simulation program indicate that the circuit design is theoretically correct, the design engineer then specifies the layout of the circuit on the silicon substrate. Each element in the integrated circuit is defined by a polygon in one or more masks. These masks are used to control the areas on the silicon substrate which are affected by various etching and deposition steps in the fabrication process used to produce the integrated circuit. The various polygons are inputted to a mask design program through a mask fabrication work station. It should be noted that the relative positions of the various elements on the silicon substrate as defined by these masks is, in general, significantly different from the relative positions of the various elements in the original schematic diagram inputted to the simulation program. Hence, the engineer can not merely use the input specifying the schematic diagram which was created for the simulation program to create the masks.
Once the masks have been defined, the layout is checked against the NET list data used in the simulation program using a design verification program. Typical of such programs is DRACULA program which may be obtained from ECAD, Inc. of Santa Clara, CA. This program takes as its input the layout data used to define the masks and the input data used to simulate the circuit using SPICE. In addition, the design verification program requires data specifying how each standard element in the circuit is constructed in terms of overlapping polygons on the various masks. For example, a typical field effect transistor consists of a thin line of polysilicon over a diffusion layer. The fabrication of the transistor is hence specified by polygons in the mask used to specify the diffusion layer and in the mask used to specify the polysilicon layer. Additional polygons specifying connections to this transistor will also be present in the masks used to define a metal layer. From the layout data, the design verification program generates a NET list which contains the interconnections between each of the standard elements in the integrated circuit. These standard elements are identified by "names" which are different than the "names" used in the simulation program data input. For example, transistor 1 in the simulation program data may be transistor 200 in the design verification program NET list. After constructing the NET list from the layout data, the design verification program then attempts to reconcile that list with the NET list used by the simulation program. If any inconsistencies are found, it reports these so that the layout data can be corrected.
Once the layout data has been inputted and verified, it is used to fabricate the desired integrated circuit. The resulting integrated circuit is then connected to a circuit exerciser which is used to test the circuit. The circuit exerciser provides input signals to the various input terminals of the integrated circuit and compares the signals on the various output terminals with those expected from a properly functioning circuit. If this test procedure indicates that the integrated circuit is not operating in accordance with its design, an engineer must determine the cause of the malfunction. Such a malfunction can result from either design or fabrication errors.
If the engineer were faced with the problem of debugging a circuit made from individual components such as transistors and resistors connected by wires, he could verify that each circuit element was present and then measure the potential as function of time at the inputs and outputs of each of the circuit elements to determine which elements were defective, if any. Performing the analogous operations on an integrated circuit is complicated by the minute size of the individual circuit elements and conductors connecting them. In principle, small mechanical probes connected to an oscilloscope or other potential measuring system can be used to measure the potential on a specific conductor. However, it is difficult to position such mechanical probes on a conductor without damaging the conductor. Furthermore, such mechanical probes may capacitively load the circuit being measured and hence alter the potential which the engineer wishes to measure. As a result, electron beam test probe systems have been developed to perform this type of measurement.
Prior art electron beam test probe systems are essentially modified scanning electron microscopes. They consist of an electron beam, a means for imaging the electron beam at a point on the integrated circuit, and a means for measuring the energy distribution of electrons leaving the point in question on the integrated circuit in response to the electron beam bombardment thereof. The electron beam test probe system may either be used as a scanning electron microscope or as a means for measuring the potential at a selected point on the surface of the integrated circuit. By using the electron beam test probe system in a scanning electron microscope mode, an image of the surface of the integrated circuit may be obtained and compared with the masks used to fabricate the integrated circuit in question. Such images allow the operator to check for obvious fabrication errors such as a missing conductor joining two circuit elements. By directing the electron beam at a conductor and examining the energy distribution of the secondary electrons produced in response to the electron beam bombardment of the conductor, the potential on the conductor at the point of bombardment may be deduced and compared with the expected potential at that point.
Because prior art electron beam test probe systems are essentially scanning electron microscopes, they have several problems which have limited their usefulness as circuit debugging tools. First, the means provided for mounting and positioning the integrated circuit with respect to the electron beam and detector are inadequate. The typical prior art electron beam test probe system consists of a scanning electron microscope and a stage for holding the integrated circuit under examination. The stage is used to hold the integrated circuit being examined and to move the integrated circuit relative to the electron beam. This movement is necessary, since the field of view of a scanning electron microscope is not sufficiently large to allow the entire integrated circuit to be viewed at once. In addition to holding the integrated circuit, this stage must also hold a probe card which contains the electrodes which are used to provide power and signals to the integrated circuit under test. The use of this stage for both of these functions leads to problems in maintaining the electrical connections to the integrated circuit under test. This probe card contains a number of small mechanical probes which must be precisely positioned on pads located on the periphery of the integrated circuit. Once positioned, the probe card and integrated circuit must be moved as a unit with no relative movement between them. Any movement of the integrated circuit relative to the probe card could result in the electrical connections provided by the probe card being interrupted. Such precise joint movement is difficult to obtain, since the probe card also contains wires which are connected to the circuit exerciser through the walls of the electron beam test probe system vacuum chamber. If one attempts to move the probe card and integrated circuit together, the forces applied to the probe card by these wires often results in movement of the probe card relative to the integrated circuit.
This problem is made still worse by the limited space available for the specimen being examined in the typical prior art system. Typically, the scanning electron microscope portion of the electron beam test probe system is mounted on top of a specimen chamber which in turn is mounted on a horizontal work surface. Since the electron microscope may not be conveniently moved, the specimen must be inserted sideways into the specimen chamber. This insertion process is further complicated by the need to place the integrated circuit as close as possible to the last lens in the electron microscope electron optical system. Hence, the space available for the inserting the wafer is quite limited. As a result, one must typically position the wafer containing the integrated circuit to be examined relative to the probe card and then insert the combined wafer and probe card sideways into the specimen chamber. This must be done without moving the wafer relative to the probe card. The wafer and probe card must then be attached to the stage for positioning relative to the electron beam. At best this is an awkward procedure.
Second, it is difficult to locate the point on the integrated circuit which corresponds to a given point in the schematic diagram of the circuit. At the commencement of the debugging procedure, the test engineer has only the results of the circuit exerciser tests to guide him in locating the source of the malfunction. These results are used to guess the most likely point in the schematic diagram of the circuit at which the malfunctioning component is located. He must then determine the physical location on the integrated circuit surface at which this component is located, position the integrated circuit so that the electron beam test probe system can view this location, and then examine the integrated circuit at the location in question. To carry out this procedure, he must first find the component in question in the NET list used in the simulation program. Then he must find the corresponding component in the layout data and determine the physical coordinates of this component relative to some known location on the integrated circuit surface such as the corner of the die on which the integrated circuit is fabricated. Finally, he must use the stage to position these coordinates within the field of view of the scanning electron microscope. If the component he has chosen is not the malfunctioning one, he must make another guess and repeat this process. In addition to being time consuming, this mode of operation is error prone, since, in general, the components in the layout data have different "names" than the corresponding components in the simulation program data.
Third, prior art electron beam test probe systems do not provide a convenient means for comparing the scanning electron microscope measurements with those expected from the layout and simulation program data. For example, once the desired point on the integrated circuit is located and an image of the surface created, the test engineer must compare it with the image expected from the layout data to determine if the components were correctly fabricated. At best, he has a copy of the masks generated from this data. Hence, he must compare an image on a cathode ray tube screen showing a small portion of the integrated circuit with a drawing of the entire mask on a piece of paper. Such visual comparisons are difficult to make.
Finally, the prior art electron beam test probe systems do not lend themselves to automated debugging. Since these systems do not include the layout and simulation program data used in the design and fabrication of the integrated circuit being tested, they must rely on the test engineer to determine each point to be examined using the above described time consuming procedures.
Broadly, it is an object of the present invention to provide an improved electron beam test probe system.
It is a further object of the present invention to provide an electron beam test probe system which allows locations on the integrated circuit under test to be specified with respect to the schematic diagram used in creating the integrated circuit.
It is a still further object of the present invention to provide an electron beam test probe system which is capable of automated circuit debugging.
It is yet another object of the present invention to provide an electron beam test probe system which allows the integrated circuit to be positioned relative to the scanning electron microscope without the danger of interrupting the probe card connections to the integrated circuit.
It is yet another object of the present invention to provide an electron beam test probe system which allows the test engineer to quickly compare the scanning electron microscope measurements with the results expected from the circuit and layout data used to fabricate the integrated circuit under test.
These and other objects of the present invention will become apparent from the following detailed description of the present invention and the accompanying drawings.